With the ever increasing demand for high data rates in consumer electronics, systems are typically pushed to utilize higher frequencies in e.g. massive multiple input, multiple output (MIMO) systems.
One main limitation of using a multiple antenna architecture is the complexity and high cost of the hardware in the radio frequency (RF) section, which typically increases with an increase in the number of antennas.
The hardware of a typical MIMO transceiver is partitioned into separate blocks, wherein each block is typically put on separate chips. According to an example, digital baseband (BB) functionality is put on one chip, RF-components such as mixers on a second chip, and power amplifiers on a third chip, while the antennas may be implemented separately.
Having multiple antennas typically requires having multiple signal paths, one for each antenna, between at least some of the hardware blocks which typically results in complex and bulky implementations, especially for radio frequency signals.
In some cases, a single signal path may be used to convey multiple signals between the antenna array and the hardware blocks which typically results in tough requirements on the signal path regarding distortion and separation of the signals.
Furthermore, the scalability of the system is limited since adding, removing, or rearranging antennas results in complex and costly processes of adding, removing, or rearranging hardware blocks.
Therefore, there is a need for hardware solutions enabling utilization of MIMO systems comprising multiple antennas while keeping implementations with an as low circuit foot print as possible without affecting the performance.